1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit in which an internal operating voltage is changed.
2. Description of the Related Art
In order to reduce the power consumption of semiconductor integrated circuits, voltage levels are generally optimized. With the development of the semiconductor process technology, processors or the like are now manufactured with a technology that achieves fine patterns such as 0.13 micrometers or less. In such a case, leak currents that are conventionally regarded as errors account for a significant proportion that can no longer be ignored. The leak currents not only flow all the time regardless of the active/inactive operating state of processors, but also have such characteristics that the amount of currents increases in response to a rise in the internal operating voltage. Further, an increase in chip temperature responsive to the rise of the operating voltage also results in an increase in the leak currents. Because of this, the presence of leak currents is a major issue that needs to be addressed to achieve low power consumption.
In order to keep the influence of leak currents to a minimum, a generally employed method lowers the internal operating voltage to reduce the leak currents during a period in which the processor or the like do not need to operate at high speed, and raises the internal voltage during a period in which high-speed operation is required. In such technology, the voltage level may not be changed at once from a given voltage level to another voltage level, but may be changed gradually in a stepwise manner by the units of small voltage steps while spending an extended period of time, thereby keeping the influence of voltage changes to a minimum. In order to implement such voltage control, there is a need for a chip to be informed of the lower voltage limit at which proper operation is possible. When the internal operating voltage is to be lowered, the control of voltages has to insure that the internal operating voltage does not drop below this lower voltage limit. If the voltage goes down below this lower voltage limit, the delay of semiconductor devices making up the processor increases, thereby presenting a risk of the processor failing to properly perform the execution of instructions and thus suffering a hangup.
Patent Document 1 discloses an invention that provides a voltage testing circuit for an operation unit inside a CPU, and that tests the operation unit while lowering the voltage little by little, thereby determining the lowest voltage at which the operation unit can properly operate. Patent Document 2 discloses a technology that can be used to obtain optimum voltage levels supplied to a plurality of processors implemented on a system board. A voltage margin test is conducted with respect to each of the processors at the time of power-on of the system, thereby supplying optimum voltage levels from the voltage source to each of the processors.
Further, Non-patent Document 1 shoes a general trend of recent technologies regarding the dynamic control of an operating frequency and an internal operating voltage of a processor by use of program instructions in response to a required performance level.
[Patent Document 1] Japanese Patent Application Publication No. 11-203163
[Patent Document 2] Japanese Patent Application Publication No. 2001-34502
[Non-patent Document 1] “Dynamic Power Management for Embedded Systems”, [online], Nov. 19, 2002, IBM, [searched on 2004, Apr. 27], Internet <URL: http://www.research.ibm.com/arl/projects/papers/DPM_V1.1.pdf>
When the voltage is gradually changed, increasing the internal voltage does not present a problem since a state transition is made toward the improvement of operating conditions of the CPU. Decreasing the internal voltage, on the other hand, presents a risk of the processor failing to perform the execution of instructions and suffering a hangup. Processors manufactured by semiconductor process have performance variation due to process variation. If it is desired to change the internal voltage dynamically while ensuring safety, a voltage range that permits proper operation needs to be identified in advance with respect to individual processors, and the voltage needs to be controlled within this voltage range while maintaining a sufficient margin.
Semiconductor integrated circuits may have the performance thereof deteriorating due to factors such as a temperature increase even during an ongoing operation. A range that permits proper operation may differ depending on operating conditions. A voltage range that is identified under certain operating conditions as permitting proper operation may no longer allow proper operation after a change in the operating conditions. In order to avoid such shortcomings, there may be a need to provide an excessively large margin.
Accordingly, there is a need for a semiconductor integrated circuit that can set an optimum voltage level in response to chip-specific operating characteristics as well as environment-specific real-time operating characteristics so as to prevent malfunctions such as a hangup when changing the operating voltage of a processor dynamically.